Referring to FIGS. 1 and 2, there is shown an image sensor of the prior art having a n-type buried channel 10 built into a p-type well 20. The buried channel 10 is covered by CCD gates 30 of either the 2,3, or four-based architecture (the two-phase architecture is shown here). The last clocked CCD gate 30b is isolated from the n-type floating diffusion amplifier input 40 by an output gate 50 which is not clocked. The floating diffusion 40 is periodically reset to a reference voltage level by a reset gate 60 forming an NMOS transistor between the floating diffusion 40 and the reset drain 70.
Referring to FIG. 3, there is shown a timing sequence for the image sensor of FIG. 1 for converting a charge packet of electrons from the CCD to a measurable voltage. At times T0, the reset gate 60 is clocked high. This turns on the reset transistor and resets the floating diffusion 40 to the reset drain reference voltage. Then at time T1, the reset gate 60 is clocked low. Capacitive coupling between the reset gate 60 and the floating diffusion 40 causes the floating diffusion voltage 40 to be pushed to a more negative voltage when the reset gate 60 is turned off. The floating diffusion 40 voltage then remains stable and is sampled at time T2. Then at time T3, the CCD clocks 30a and 30b changes levels and transfers a new charge packet over the output gate 50 and onto the floating diffusion 40. The magnitude of the voltage change at time T3 on the floating diffusion 40 is proportional to the size of the charge packet and floating diffusion capacitance. The new voltage on the floating diffusion 40 is sampled at time T4, and then the timing cycle is repeated.
Although the presently known and utilized CCD is satisfactory, it includes drawbacks. The shortcoming of this CCD output sensing structure is that the reset clock pulse is generated external to the image sensor. Therefore, the reset clock must travel through the image sensor input, bonding wire, and metal wiring before reaching the reset gate. At higher frequencies, for example frequencies greater than 30 MHz, the path from the reset clock driver to the reset gate has substantial capacitance, resistance and inductance which degrades the shape of the reset pulse as shown in FIG. 4.